Tutorials

The microelectronics industry has undergone significant innovation in recent years. The decades-long technology roadmap that involved planar transistor scaling has nowadays evolved into a search for optimal geometries and materials beyond silicon. With this change, circuit designers and fabrication engineers can no longer enjoy the benefits of decades of experimental information on silicon. Technology computer-aided design (TCAD) and design-technology co-optimization (DTCO) strategies need to adapt to include the search for novel materials through a multi-scale modeling approach, where the atomistic behavior of a material informs design decisions. Furthermore, with a continued reduction of design margins, process variability is becoming a significant concern. Understanding equipment-level and across-wafer variation is paramount. However, current implementations of physical deposition and etching models do not provide a direct link to equipment inputs.

This talk will discuss the current state of process simulation and emulation, and what we are currently investigating and developing to assist the microelectronics industry, which includes both semiconductor manufacturers and electronic design automation (EDA) vendors. In this tutorial, we will cover several aspects essential to modeling semiconductor fabrication. The inclusion of TCAD and DTCO during the design process has become invaluable and for these, both time-discretized physical models and quick geometric emulations have a role to play. The tutorial will also discuss how machine learning is helping merge feature-scale modeling approaches with reactor-level inputs and equipment variability. The applied method can provide semiconductor manufacturers a virtual copy of their equipment, which is directly linked to physical and empirical deposition and etching models. Ultimately, this creates a pathway towards a digital DTCO strategy for design discovery while reducing cost, time, and the environmental impact of a design cycle by reducing the heavy reliance on experimental wafer fabrication.